This invention generally relates to a filter circuit configuration for digital signal processing and, more particularly, to a binary rate multiplier (BRM) filter in a bi-quad configuration.
Analog-to-digital converters (ADCs) are well known in the art, and are configured to convert an analog signal to a digital signal. The sigma delta conversion technique is a low cost ADC conversion method that provides both high dynamic range and flexibility in converting low bandwidth input signals.
In order to obtain a high quality digital signal as a result of AD conversion, various techniques may be used to reduce noise or error. For example, an electronic filter may be used to distribute the converter quantization error or noise such that it is very low in the band of interests. Over sampling is another method of decreasing the quantization noise by sampling the input signal at a frequency much greater than the Nyquist frequency (two times the input signal bandwidth). Similarly, decimation reduces the input signal sampling rate without loosing information. An on-chip digital filter can also be used to attenuate signals and noise that are outside the band of interest according to the parameters of a particular application.
An electronic filter is designed to transmit some range of signal frequencies while rejecting others, i.e., to emphasize or “pass” certain frequencies and attenuate or “stop” others. A digital filter has two types depending on whether the impulse response contains a finite or infinite number of nonzero terms. A finite impulse response (FIR) filter can be designed to be linear phase, a characteristics that ensures that a filter has a constant group delay independent of frequency. An infinite impulse response digital filter requires much less computation to implement than a FIR filter with a corresponding frequency response. However, IIR filters cannot generally achieve an adequate linear-phase response and are more susceptible to finite word length effects, which may result in round-off noise, coefficient quantization error and overflow oscillations. In addition, FIR filters require more bit width, up to 50 bits in practice, which can be burdensome to a circuit. “Bit width” refers to the width of the bits that must be processed in parallel and is the “data path width” of the digital implementation.
Therefore, there exists a need for a filter that has an accuracy similar to that of a FIR filter, but that requires less bit width.